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ALC888S-GR
7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC WITH TWO INDEPENDENT S/PDIF-OUT
DATASHEET
Rev. 1.1 05 February 2007 Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw
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ALC888S Datasheet
COPYRIGHT (c)2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.
TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT This document is intended for the hardware and software engineer's general information on the Realtek ALC888S Audio Codec IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision 1.0 1.1 Release Date 2007/01/15 2007/02/05 Summary First release. Update section 12 Ordering Information, page 76. Correct ADC support data in section 2.1 Hardware Features, page 2.
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Table of Contents
1. 2. General Description .................................................................................................... 1 Features ........................................................................................................................ 2
2.1. 2.2. HARDWARE FEATURES.....................................................................................................................2 SOFTWARE FEATURES ......................................................................................................................3
3. 4. 5. 6.
System Applications .................................................................................................... 3 Block Diagram ............................................................................................................. 4
4.1. 5.1. 6.1. 6.2. 6.3. 6.4. ANALOG INPUT/OUTPUT UNIT .........................................................................................................5 GREEN PACKAGE AND VERSION IDENTIFICATION ............................................................................6 DIGITAL I/O PINS .............................................................................................................................7 ANALOG I/O PINS.............................................................................................................................7 FILTER/REFERENCE ..........................................................................................................................8 POWER/GROUND ..............................................................................................................................8 LINK SIGNALS ..................................................................................................................................9
Signal Definitions .................................................................................................................................................10 Signaling Topology ............................................................................................................................................... 11
Pin Assignments........................................................................................................... 6 Pin Descriptions........................................................................................................... 7
7.
High Definition Audio Link Protocol ........................................................................ 9
7.1.
7.1.1. 7.1.2.
7.2.
7.2.1. 7.2.2. 7.2.3. 7.2.4. 7.2.5.
FRAME COMPOSITION.....................................................................................................................12
Outbound Frame - Single SDO............................................................................................................................12 Outbound Frame - Multiple SDOs.......................................................................................................................13 Inbound Frame - Single SDI ................................................................................................................................14 Inbound Frame - Multiple SDIs...........................................................................................................................15 Variable Sample Rates..........................................................................................................................................15
7.3.
7.3.1. 7.3.2. 7.3.3.
RESET AND INITIALIZATION............................................................................................................18
Link Reset .............................................................................................................................................................18 Codec Reset ..........................................................................................................................................................19 Codec Initialization Sequence ..............................................................................................................................20
7.4.
7.4.1. 7.4.2.
VERB AND RESPONSE FORMAT.......................................................................................................20
Command Verb Format ........................................................................................................................................20 Response Format..................................................................................................................................................22
7.5.
POWER MANAGEMENT ...................................................................................................................23 VERB - GET PARAMETERS (VERB ID=F00H) .................................................................................25
Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................25 Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................25 Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................26 Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) ...........................................................26 iii Track ID: JATR-1076-21 Rev. 1.1
8.
Supported Verbs and Parameters............................................................................ 25
8.1.
8.1.1. 8.1.2. 8.1.3. 8.1.4.
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8.1.5. 8.1.6. 8.1.7. 8.1.8. 8.1.9. 8.1.10. 8.1.11. 8.1.12. 8.1.13. 8.1.14. 8.1.15. 8.1.16.
Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................27 Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................27 Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................28 Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................29 Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................30 Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................31 Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................31 Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................32 Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................32 Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h) .......................................................32 Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ...............................................................33 Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...................................................33
8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.8. 8.9. 8.10. 8.11. 8.12. 8.13. 8.14. 8.15. 8.16. 8.17. 8.18. 8.19. 8.20. 8.21. 8.22. 8.23. 8.24. 8.25. 8.26. 8.27. 8.28. 8.29. 8.30. 8.31. 8.32. 8.33. 8.34. 8.35. 8.36.
VERB - GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................34 VERB - SET CONNECTION SELECT (VERB ID=701H) .....................................................................34 VERB - GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................35 VERB - GET PROCESSING STATE (VERB ID=F03H)........................................................................39 VERB - SET PROCESSING STATE (VERB ID=703H) ........................................................................39 VERB - GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................40 VERB - SET COEFFICIENT INDEX (VERB ID=5H)............................................................................40 VERB - GET PROCESSING COEFFICIENT (VERB ID=CH).................................................................41 VERB - SET PROCESSING COEFFICIENT (VERB ID=4H) ..................................................................41 VERB - GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................42 VERB - SET AMPLIFIER GAIN (VERB ID=3H).................................................................................44 VERB - GET CONVERTER FORMAT (VERB ID=AH)........................................................................45 VERB - SET CONVERTER FORMAT (VERB ID=2H) .........................................................................46 VERB - GET POWER STATE (VERB ID=F05H)................................................................................47 VERB - SET POWER STATE (VERB ID=705H).................................................................................48 VERB - GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................48 VERB - SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................49 VERB - GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................50 VERB - SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................51 VERB - GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................52 VERB - SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................52 VERB - GET PIN SENSE (VERB ID=F09H) ......................................................................................53 VERB - EXECUTE PIN SENSE (VERB ID=709H) ..............................................................................53 VERB - GET CONFIGURATION DEFAULT (VERB ID=F1CH) ...........................................................54 VERB - SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3).............................................................................................................................54 VERB - GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................55 VERB - SET BEEP GENERATOR (VERB ID=70AH) ........................................................................55 VERB - GET GPIO DATA (VERB ID=F15H) ...................................................................................56 VERB - SET GPIO DATA (VERB ID=715H)....................................................................................56 VERB - GET GPIO ENABLE MASK (VERB ID=F16H).....................................................................57 VERB - SET GPIO ENABLE MASK (VERB ID=716H)......................................................................57 VERB - GET GPIO DIRECTION (VERB ID=F17H)...........................................................................58 VERB - SET GPIO DIRECTION (VERB ID=717H)............................................................................58 VERB - GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ...........................59 VERB - SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ............................59
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8.37. 8.38. 8.39. 8.40. 8.41.
VERB - FUNCTION RESET (VERB ID=7FFH) ..................................................................................60 VERB - GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) ..............60 VERB - SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................62 VERB - GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H) ......................................63 VERB - SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR [7:0]) ..................................................................................................................64 DC CHARACTERISTICS ...................................................................................................................65
Absolute Maximum Ratings ..................................................................................................................................65 Threshold Voltage .................................................................................................................................................65 Digital Filter Characteristics ...............................................................................................................................66 S/PDIF Input/Output Characteristics...................................................................................................................66
9.
Electrical Characteristics ......................................................................................... 65
9.1.
9.1.1. 9.1.2. 9.1.3. 9.1.4.
9.2.
9.2.1. 9.2.2. 9.2.3. 9.2.4.
AC CHARACTERISTIC .....................................................................................................................67
Link Reset and Initialization Timing.....................................................................................................................67 Link Timing Parameters at the Codec ..................................................................................................................68 S/PDIF Output and Input Timing .........................................................................................................................69 Test Mode..............................................................................................................................................................69
9.3. 10.1. 10.2. 10.3. 10.4. 10.5. 10.6.
ANALOG PERFORMANCE ................................................................................................................70 FILTER CONNECTION......................................................................................................................71 ONBOARD FRONT PANEL HEADER CONNECTION ...........................................................................72 JACK CONNECTION ON REAR PANEL ..............................................................................................73 S/PDIF INPUT/OUTPUT CONNECTION ............................................................................................73 SECONDARY S/PDIF-OUT CONNECTED TO HDMI TX CONNECTOR..............................................74 DIFFERENTIAL ANALOG CD USED AS LINE LEVEL INPUT ..............................................................74
10. Application Circuits .................................................................................................. 71
11. Mechanical Dimensions ............................................................................................ 75 12. Ordering Information ............................................................................................... 76
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Digital I/O Pins ...........................................................................................................................7 Analog I/O Pins...........................................................................................................................7 Filter/Reference...........................................................................................................................8 Power/Ground .............................................................................................................................8 Link Signal Definitions.............................................................................................................10 HDA Signal Definitions............................................................................................................10 Defined Sample Rate and Transmission Rate...........................................................................16 48kHz Variable Rate of Delivery Timing .................................................................................16 44.1kHz Variable Rate of Delivery Timing ..............................................................................17 40-Bit Commands in 4-Bit Verb Format...................................................................................20 40-Bit Commands in 12-Bit Verb Format.................................................................................20 Supported Commands...............................................................................................................21 Supported Parameters ...............................................................................................................22 Solicited Response Format .......................................................................................................22 Unsolicited Response Format ...................................................................................................23 System Power State Definitions ...............................................................................................23 Power Controls in NID 01h ......................................................................................................23 Powered Down Conditions .......................................................................................................24 Verb - Get Parameters (Verb ID=F00h) ...................................................................................25 Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h) ...................................................25 Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................25 Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................26 Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................26 Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................27 Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................27 Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................28 Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................29 Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................30 Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....31 Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...31 Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................32 Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................32 Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..............................32 Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ......................................33 Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) .........................33 Verb - Get Connection Select Control (Verb ID=F01h)...........................................................34 Verb - Set Connection Select (Verb ID=701h) .........................................................................34 Verb - Get Connection List Entry (Verb ID=F02h)..................................................................35 Verb - Get Processing State (Verb ID=F03h) ...........................................................................39 Verb - Set Processing State (Verb ID=703h)............................................................................39 Verb - Get Coefficient Index (Verb ID=Dh).............................................................................40 Verb - Set Coefficient Index (Verb ID=5h) ..............................................................................40 Verb - Get Processing Coefficient (Verb ID=Ch).....................................................................41 Verb - Set Processing Coefficient (Verb ID=4h)......................................................................41
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Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83.
Verb - Get Amplifier Gain (Verb ID=Bh) ................................................................................42 Verb - Set Amplifier Gain (Verb ID=3h)..................................................................................44 Verb - Get Converter Format (Verb ID=Ah) ............................................................................45 Verb - Set Converter Format (Verb ID=2h)..............................................................................46 Verb - Get Power State (Verb ID=F05h) ..................................................................................47 Verb - Set Power State (Verb ID=705h) ...................................................................................48 Verb - Set Converter Stream, Channel (Verb ID=706h)...........................................................49 Verb - Get Pin Widget Control (Verb ID=F07h) ......................................................................50 Verb - Set Pin Widget Control (Verb ID=707h) .......................................................................51 Verb - Get Unsolicited Response Control (Verb ID=F08h) .....................................................52 Verb - Set Unsolicited Response Control (Verb ID=708h) ......................................................52 Verb - Get Pin Sense (Verb ID=F09h)......................................................................................53 Verb - Execute Pin Sense (Verb ID=709h)...............................................................................53 Verb - Get Configuration Default (Verb ID=F1Ch) .................................................................54 Verb - Set Configuration Default Bytes 0, 1, 2, 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) ............................................................54 Verb - Get BEEP Generator (Verb ID= F0Ah).........................................................................55 Verb - Set BEEP Generator (Verb ID= 70Ah)..........................................................................55 Verb - Get GPIO Data (Verb ID= F15h) ..................................................................................56 Verb - Set GPIO Data (Verb ID= 715h) ...................................................................................56 Verb - Get GPIO Enable Mask (Verb ID= F16h) .....................................................................57 Verb - Set GPIO Enable Mask (Verb ID=716h).......................................................................57 Verb - Get GPIO Direction (Verb ID=F17h)............................................................................58 Verb - Set GPIO Direction (Verb ID=717h).............................................................................58 Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) ..................................59 Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) ...................................59 Verb - Function Reset (Verb ID=7FFh)....................................................................................60 Verb - Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh) ........................60 Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................62 Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) ........................................63 Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])...............................................................................................................64 Absolute Maximum Ratings .....................................................................................................65 Threshold Voltage .....................................................................................................................65 Digital Filter Characteristics .....................................................................................................66 S/PDIF Input/Output Characteristics ........................................................................................66 Link Reset and Initialization Timing ........................................................................................67 Link Timing Parameters at the Codec.......................................................................................68 S/PDIF Output and Input Timing..............................................................................................69 Analog Performance .................................................................................................................70 Ordering Information ................................................................................................................76
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Block Diagram ..........................................................................................................................4 Analog Input/Output Unit .........................................................................................................5 Pin Assignments ........................................................................................................................6 HDA Link Protocol ...................................................................................................................9 Bit Timing ...............................................................................................................................10 Signaling Topology .................................................................................................................11 SDO Outbound Frame.............................................................................................................12 SDO Stream Tag is Indicated in SYNC ..................................................................................12 Striped Stream on Multiple SDOs...........................................................................................13 SDI Inbound Stream................................................................................................................14 SDI Stream Tag and Data ........................................................................................................14 Codec Transmits Data Over Multiple SDIs.............................................................................15 Link Reset Timing...................................................................................................................19 Codec Initialization Sequence.................................................................................................20 Link Reset and Initialization Timing.......................................................................................67 Link Signals Timing ................................................................................................................68 Output and Input Timing .........................................................................................................69 Filter Connection.....................................................................................................................71 Front Panel Header Connection ..............................................................................................72 Jack Connection on Rear Panel...............................................................................................73 S/PDIF Input/Output Connection............................................................................................73 Secondary S/PDIF-OUT Connected to HDMI Tx Connector.................................................74 Differential Analog CD Used as Line Level Input..................................................................74
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1.
General Description
The ALC888S, an advanced version of the ALC888, is a high-performance 7.1+2 Channel High Definition Audio Codec that meets Microsoft Windows Vista (WLP 3.08) premium requirements. It provides ten DAC channels that simultaneously support 7.1 sound playback, plus independent stereo sound output (multiple streaming) through the front panel stereo outputs. The ALC888S integrates two stereo ADCs that can support a stereo microphone, and feature Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology. All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog output. All analog IOs can be re-tasked according to user's definitions, or automatically switched depending on the connected device type. Support for 16/20/24-bit S/PDIF input and output offers easy connection of PCs to high-quality consumer electronic products such as digital decoders and speakers. The ALC888S incorporates Realtek proprietary converter technology to achieve 97dB dynamic range playback quality and 90dB dynamic range recording quality, and is designed for Windows Vista premium desktop and laptop systems. The ALC888S features extra (secondary) S/PDIF-OUT outputs and converters that transport digital audio output to a High Definition Media Interface (HDMI) transmitter (becoming more common in high-end PCs). The ALC888S supports host/soft audio from the Intel ICH series chipset, and also from any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional audio, and optional Dolby(R) Digital Live, DTS(R) CONNECTTM, and Dolby(R) Home Theater programs, the ALC888S provides an excellent home entertainment package and game experience for PC users.
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2.
Features
High-performance DACs with 97dB SNR (A-Weighting), ADCs with 90dB SNR (A-Weighting) Meets performance requirements for Microsoft WLP 3.08 Premium desktop and mobile PCs Ten DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels of independent stereo sound output (multiple streaming) through the front panel output Two stereo ADCs support 16/20-bit PCM format, one for stereo microphone, one for legacy mixer recording All DACs supports 44.1k/48k/96k/192kHz sample rate All ADCs support 44.1k/48k/96k sample rate Two independent 16/20/24-bit S/PDIF-OUT converters support 44.1k/48k/88.2k/96k/192kHz sample rate, one for nominal digital audio, the other one for digital audio output to a HDMI transmitter One 16/20/24-bit S/PDIF-IN converter supports 44.1k/48k/96k/192kHz sample rate Up to four channels of analog microphone array input are supported for AEC/BF application Supports stereo digital microphone interface for improved voice quality High-quality analog differential CD input Supports external PCBEEP input and built-in digital BEEP generator Software selectable 2.5V/3.75V VREFOUT Two jack detection pins each designed to detect up to 4 jacks Supports legacy analog mixer architecture Wide range (-80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain Software selectable boost gain (+10/+20/+30dB) for analog microphone input All analog jacks are stereo input and output re-tasking for analog plug & play Built-in headphone amplifiers for each re-tasking jack Two digital GPIOs (General Purpose Input and Output) and one analog GPIO (AGPIO) for customized applications The analog GPIO (AGPIO) can be a jack detection pin when the analog CD input is used as line level input and configured to support jack detection, which is driver independent Supports anti-pop mode when analog power AVDD is on and digital power is off 48-pin LQFP `Green' package
2.1. Hardware Features
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2.2. Software Features
Meets Microsoft WLP 3.08 audio requirements WaveRT-based audio function driver for Windows Vista EAXTM 1.0 & 2.0 compatible Direct Sound 3DTM compatible A3DTM compatible I3DL2 compatible HRTF 3D Positional Audio Emulation of 26 sound environments to enhance gaming experience 10-Band Software Equalizer Voice Cancellation and Key Shifting in Karaoke mode Realtek Media Player Realtek Configuration Panel to improve users experience for Windows Vista Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application Features Dolby(R) Digital Live and DTS(R) CONNECTTM software (Optional) Features Dolby(R) Home Theater software (Optional)
3.
System Applications
Desktop multimedia PCs Notebook PCs Information appliances (IA) e.g., set-top box
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4.
PCM-5
25h SRC SRC SRC
CLfe DAC
DAC Fout1 DAC DAC SideSurr DAC DAC VOL M I/OA 15h VOL M I/OA VOL
SurrFront SideSurr CLfe Fout Boost
26h 0Fh M M M M M M M M M I/OA VOL M M M I/OA 16h 17h VOL
Fout SideSurr CLfe Surr Front
Surr Front SideSurr CLfe Fout Boost Surr Front SideSurr CLfe Fout Boost
PCM-4
05h 04h 03h SRC SRC 0Bh BEEP Gen DAC Front DAC 0Ch DAC Surr DAC 02h
Front Surr SideSurr CLfe Fout Boost
SIDESURR(Port-H)
PCM-3
0Eh 0Dh
CEN/LFE(Port-G) SURR(Port-A) FRONT(Port-D) BEEP CD-IN
1Dh 1Ch 1Bh 14h
PCM-2
Block Diagram
7.1+2 Channel High Definition Audio Codec
VOL VOL VOL VOL VOL VOL VOL VOL VOL VOL
Front Surr SideSurr CLfe Fout Boost
PCM-1
Figure 1.
M
M
Digital Interface
Block Diagram
09h SRC
M
4
ADC VOL M
M M M M M M M M M M
1 22h
M M M M M M M M M M
I/OA M
LINE2(Port-E)
Surr Front SideSurr CLfe Fout Boost
Parameters
08h SRC ADC VOL M
I/OA M 23h
1Ah
LINE1(Port-C)
Front Surr SideSurr CLfe Fout Boost
M M M M M M M M M M
I/OA M
MIC2(Port-F)
Surr Front SideSurr CLfe Fout Boost
19h
I/OA
MIC1(Port-B) S/PDIF-OUT 1Eh
18h
SP-OUT DATA SP-IN PCM Secondary SP-OUT DATA
06h 0Ah 10h
S/PDIF-OUT S/PDIF-IN S/PDIF-OUT
S/PDIF-IN 1Fh S/PDIF-OUT2
11h
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ALC888S Datasheet
4.1. Analog Input/Output Unit
Pin Complex widgets NID=14h~1Bh are re-tasking IOs.
R A EN_OBUF EN_AMP EN_OBUF
Output_Signal_Left Output_Signal_Right Input_Signal_Left Input_Signal_Right
R
Left Right
EN_IBUF
Figure 2.
Analog Input/Output Unit
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5.
Pin Assignments
FRONT-R (Port-D) FRONT-L (Port-D) Sense B AGPIO MIC1-VREFO-R LINE2-VREFO MIC2-VREFO LINE1-VREFO MIC1-VREFO-L VREF AVSS1 AVDD1
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
PIN37-VREFO AVDD2 SURR-L (Port-A-L) JDREF SURR-R (Port-A-R) AVSS2 CENTER (Port-G-L) LFE (Port-G-R) SIDE-L (Port-H-L) SIDE-R (port-H-R) SPDIFI/EAPD SPDIFO
37 38 39 40 41 42 43 44 45 46 47 48
ALC888S
LLLLLLL TXXXV
1 2 3 4 5 6 7 8 9 10 11 12
LINE1-R (Port-C-R) LINE1-L (Port-C-L) MIC1-R (Port-B-R) MIC1-L (Port-B-L) CD-R CD-GND CD-L MIC2-R (Port-F-R) MIC2-L (Port-F-L) LINE2-R (Port-E-R) LINE2-L (Port-E-L) Sense A
5.1. Green Package and Version Identification
Green package is indicated by a `G' in the location marked `T' in Figure 3. The version number is shown in the location marked `V'.
7.1+2 Channel High Definition Audio Codec
DVDD GPOI0/DMIC-CLK/SPDIFO2 GPIO1/DMIC-DATA DVSS SDATA-OUT BCLK DVSS SDATA-IN DVDD-IO SYNC RESET# PCBEEP
Figure 3. Pin Assignments 6
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ALC888S Datasheet
6.
Pin Descriptions
Table 1. Digital I/O Pins Description Characteristic Definition H/W reset Vt=0.5*DVDD Sample Sync (48kHz) Vt=0.5*DVDD 24MHz Bit clock input Vt=0.5*DVDD Serial TDM data input Vt=0.5*DVDDIO Serial TDM data output Vt=0.5*DVDDIO, VOH=DVDDIO, VOL=DVSS S/PDIF Input / VIL=1.45V, VIH=1.85V / Signal to power down ext. amp VOH=DVDD, VOL=DVSS 48 S/PDIF output Output has 12mA@75 driving capability VOH=DVDD, VOL=DVSS 2 General Purpose Input/Output 0 Input: Vt=(2/3)*DVDD Clock output to digital MIC Output: VOH=DVDD, VOL=DVSS Secondary S/PDIF output Output: VOH=DVDD, VOL=DVSS 3 General Purpose Input/Output 1 Input: Vt=(2/3)*DVDD Serial data from digital MIC Output: VOH=DVDD, VOL=DVSS Total: 9 Pins
6.1. Digital I/O Pins
Name RESET# SYNC BITCLK SDATA-OUT SDATA-IN SPDIFI / EAPD SPDIFO GPIO0 / DMIC-CLK / SPDIFO2 GPIO1 / DMIC-DATA Type I I I I O I/O O I/O Pin 11 10 6 5 8 47
I/O
6.2. Analog I/O Pins
Name LINE2-L LINE2-R MIC2-L MIC2-R CD-L CD-G CD-R MIC1-L MIC1-R LINE1-L LINE1-R PCBEEP FRONT-L FRONT-R Table 2. Analog I/O Pins Type Pin Description Characteristic Definition nd IO 14 2 line input left channel Analog input/output, default is input (JACK-E) IO 15 2nd line input right channel Analog input/output, default is input (JACK -E) nd IO 16 2 stereo microphone input Analog input/output, default is input (JACK -F) left channel IO 17 2nd stereo microphone input Analog input/output, default is input (JACK -F) right channel I 18 CD input left channel Analog input, 1.6Vrms of full scale input I 19 CD input reference ground Analog input, 1.6Vrms of full scale input I 20 CD input right channel Analog input, 1.6Vrms of full scale input Analog input/output, default is input (JACK -B) IO 21 1st stereo microphone input left channel Analog input/output, default is input (JACK -B) IO 22 1st stereo microphone input right channel IO 23 1st line input left channel Analog input/output, default is input (JACK -C) IO 24 1st line input right channel Analog input/output, default is input (JACK -C) I 12 External PCBEEP input Analog input, 1.6Vrms of full scale input IO 35 Front output left channel Analog output (JACK -D) IO 36 Front output right channel Analog output (JACK -D) 7 Track ID: JATR-1076-21 Rev. 1.1
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Type Pin Description IO 39 Surround out left channel IO 41 Surround out right channel O 43 Center output O 44 Low Frequency output O 45 Side output left channel O 46 Side output right channel I 13 Jack Detect pin l I 34 Jack Detect pin 2 IO 33 Analog general purpose I/O Characteristic Definition Analog output (JACK -A) Analog output (JACK -A) Analog output (JACK -G) Analog output (JACK -G) Analog output (JACK -H) Analog output (JACK -H) Jack resistor network input 1 Jack resistor network input 2 Input: Vt=(1/2)*AVDD1 Output: VOH=AVDD, VOL=AVSS1 Total: 23 Pins
Name SURR -L SURR -R CENTER LFE SIDE -L SIDE -R Sense A Sense B AGPIO
6.3. Filter/Reference
Name VREF MIC1-VREFO-L LINE1-VREFO MIC2-VREFO LINE2-VREFO MIC1-VREFO-R PIN37-VREFO JDREF Type O O O O O O Pin 27 28 29 30 31 32 37 Table 3. Filter/Reference Description Characteristic Definition 2.5V Reference voltage 10uf capacitor to analog ground Bias voltage for MIC1 jack 2.5V/3.75V reference voltage Bias voltage for LINE1 jack 2.5V/3.75V reference voltage Bias voltage for MIC2 jack 2.5V/3.75V reference voltage Bias voltage for LINE2 jack 2.5V/3.75V reference voltage Bias voltage for MIC1 jack 2.5V/3.75V reference voltage 2.5V/3.75V reference voltage Bias voltage for software select jack 40 Reference resistor for Jack 20K, 1% external resistor to analog ground detection Total: 8 Pins
6.4. Power/Ground
Name AVDD1 AVSS1 AVDD2 AVSS2 DVDD DVSS DVDD-IO DVSS Table 4. Type Pin Description I 25 Analog VDD I 26 Analog GND I 38 Analog VDD I 42 Analog GND I 1 Digital VDD I 4 Digital GND I 9 Digital VDD I 7 Digital GND Power/Ground Characteristic Definition Analog power for mixer and amplifier Analog ground for mixer and amplifier Analog power for DACs and ADCs Analog ground for DACs and ADCs Digital power for core Digital ground for core Digital IO power for HDA bus Digital ground for HDA bus Total: 8 Pins
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ALC888S Datasheet
7.
High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent by the HDA controller. The input and output streams, including command and PCM data, are isochronous with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
Previous Frame BCLK Frame SYNC= 8 BCLK SYNC
Tframe_sync = 20.833 s (48KHz)
Next Frame
Stream 'A' Tag (Here 'A' = 5)
Stream 'B' Tag (Here 'B' = 6)
SDO
Command Stream (40-bit data)
Stream 'A' Data
Stream 'B' Data
SDI
Response Stream (36-bit data)
Stream 'C' Tag
Stream 'C' Data (n bytes + 10-bit data)
RST#
Figure 4.
HDA Link Protocol
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7.1.1.
Item BCLK SYNC SDO
Signal Definitions
Table 5. Link Signal Definitions Description 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs. 48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA controller and connects to all codecs. Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To extend outbound bandwidth, multiple SDOs may be supported. Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA controller. The controller must support at least one SDI, and up to a maximum of 15 SDI's can be supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of BCLK. SDI can be driven by the controller to initialize the codec's ID. Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the HDA controller and connects to all codecs.
SDI
RST#
Table 6. HDA Signal Definitions Signal Name Source Type for Controller Description BCLK Controller Output Global 24.0MHz bit clock SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal SDO Controller Output Serial data output from controller SDI Codec/Controller Input/Output Serial data input from codec. Weakly pulled down by the controller RST# Controller Output Global active low reset signal
BCLK SYNC
8-Bit Frame SYNC Start of Frame
SDO SDI
7
6
5
4
3
2
1
0 999 998 997 996 995 994 993 992 991 990
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK Controller samples SDI at rising edge of BCLK
Figure 5.
Bit Timing
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7.1.2.
Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream. RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own point-to-point SDI signal(s) to the controller. Figure 6 shows the possible connections between the HDA controller and codecs: * * * * Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and codecs. Section 7.2 Frame Composition, page 12 describes the detailed outbound and inbound stream compositions for single and multiple SDOs/SDIs. The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC888S is designed to receive a single SDO stream.
SDI14 . . . SDI13 SDI2 HDA SDI1 Controller SDI0 SDO1 SDO0 SYNC BCLK RST#
. . .
7.1+2 Channel High Definition Audio Codec
SDO0 SYNC BCLK RST#
S DI0 SDO1 SDO0 SYNC BCLK RST#
SDI2 SDI1 SDI0 SDO1 SDO0 SYNC BCLK RST#
SDO0 SYNC BCLK RST#
SDI0
SDI1 SDI0
...
Codec 0 Single SDO Single SDI
Codec 1 Two SDOs Single SDI
Codec 2 Single SDO Two SDIs
Codec N Two SDOs Multiple SDIs
Figure 6.
Signaling Topology
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7.2. Frame Composition
7.2.1. Outbound Frame - Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry 96kHz samples (Figure 7). For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 8). To keep the cadence of converters bound to the same stream, samples for these converters must be placed in the same block.
Previous Frame
A 48kHz Frame is composed of Command stream and multiple Data streams Stream 'A' Tag (Here 'A' = 5) Stream 'X' Tag (Here 'X' = 6)
Next Frame
Frame SYNC
SYNC
SDO
Command Stream
Stream 'A' Data
Stream 'X' Data
0s
Sample Block(s) Block 1 Block 2 Sample 2 ... lsb .. . .. .
One or multiple blocks in a stream
Null Field
Padded at the end of Frame
Block Y
For 48kHz rate, only Block1 is included For 96kHz rate, Block1 includes (N)th time of samples, Block2 includes (N+1)th time of samples
Sample 1
Sample Z Z channels of PCM Sample
msb
msb first in a sample
Figure 7.
SDO Outbound Frame
BCLK
Stream Tag
msb SYNC
Preamble (4-Bit)
lsb
1010
Stream=10 (4-Bit) ms b Data of Stream 10
SDO
76543210 Previous Stream
Figure 8. 7.1+2 Channel High Definition Audio Codec
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ALC888S Datasheet
7.2.2.
Outbound Frame - Multiple SDOs
The HDA controller allows two SDO signals to be used to strip outbound data, completing transmission in less time to get more bandwidth. If software determines the target codec supports multiple SDO capability, it enables the `Strip Control' bit in the controller's Output Stream Control Register to initiate a specific stream (Stream `A' in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of the data stream is always carried on SDO0, the second bit on SDO1 and so forth. SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to SDO0. To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It is always transmitted on SDO0, and copied on SDO1.
Figure 9.
Striped Stream on Multiple SDOs
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7.2.3.
Inbound Frame - Single SDI
An Inbound Frame - A single SDI is composed of one 36-bit response stream and multiple data streams. Except for the initialization sequence (turnaround and address frame), the SDI is driven by the codec at each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10). The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the total length of the contiguous sample blocks within a given stream is not of integral byte length (Figure 11).
Previous Frame A 48kHz Frame is Composed of a Response Stream and Multiple Data streams Next Frame
Frame SYNC SYNC
SDI
Response Stream
Stream 'A'
Stream 'X'
0s
Null Field Stream Tag Block 1 Sample Block(s) ... ... lsb Block Y Null Pad
Padded at the end of Frame
Block 2
For 48kHz rate, only Block1 is included For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
Sample 1 Sample 2 msb ...
Sample Z Z channels of PCM Sample
msb first in a sample
Figure 10. SDI Inbound Stream
BCLK
Stream Tag Data Length in Bytes B6 B5 B4 B3 B2 B1
n-Bit Sample Block
Null Pad 0 0 0 0
Next Stream
SDI
B9
B8
B7
B0 Dn-1 Dn-2
D0
(Data Length in Bytes *8)-Bit A Complete Stream
Figure 11. SDI Stream Tag and Data
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7.2.4.
Inbound Frame - Multiple SDIs
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound stream exceeds the data transfer limits of a single SDI, the codec can divide the data into separate SDI signals, each of which operate independently, with different stream numbers at the same frame time. This is similar to having multiple codecs connected to the controller. The controller samples the divided stream into separate memory with multiple DMA descriptors, then software re-combines the divided data into a meaningful stream.
SYNC Frame SYNC SDI 0 Response Stream Tag A Stream 'A' Data A Stream 'B' SDI 1 Response Stream Tag B Data B 0s 0s Stream 'X' Stream 'Y'
Codec drives SDI0 and SDI1
Stream A, B, X, and Y are independent and have separate IDs
Figure 12. Codec Transmits Data Over Multiple SDIs
7.2.5.
Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own sample rate, independent of any other stream. The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 16, shows the recommended sample rates based on multiples or sub-multiples of one of the two base rates. Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 16, shows the delivery cadence of variable rates based on 48kHz. The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample blocks are transmitted every 160 frames. The cadence "12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)" interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame AND interleave an empty frame between non-empty frames (Table 9, page 17).
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Table 7. Defined Sample Rate and Transmission Rate 48kHz Base 44.1kHz Base 8kHz (1 sample block every 6 frames) 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames) 16kHz (1 sample block every 3 frames) 22.05kHz (1 sample block every 2 frames) 32kHz (2 sample blocks every 3 frames) 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame) 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame) 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)
(Sub) Multiple 1/6 1/4 1/3 1/2 2/3 1 2 4
Table 8. Rate Delivery Cadence 8kHz YNNNNN (repeat) 12kHz YNNN (repeat) 16kHz YNN (repeat) 32kHz Y2NN (repeat) 48kHz Y (repeat) 96kHz Y2 (repeat) 192kHz Y4 (repeat) N: No sample block in a frame Y: One sample block in a frame Yx: X sample blocks in a frame
48kHz Variable Rate of Delivery Timing Description One sample block is transmitted in every 6 frames One sample block is transmitted in every 4 frames One sample block is transmitted in every 3 frames One sample block is transmitted in every 6 frames One sample block is transmitted in every 6 frames Two sample blocks are transmitted in each frame Four sample blocks are transmitted in each frame
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Table 9. 44.1kHz Variable Rate of Delivery Timing Rate Delivery Cadence 11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat) 88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat) 174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN {11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN { - }=NNNN 22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN {11}=YNYNYNYNYNYNYNYNYNYNYN { - }=NN 44.1kHz 88.2kHz 174.4kHz 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with no sample block. 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no sample block. 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no sample block.
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7.3. Reset and Initialization
There are two types of reset within an HDA link: * * Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state Codec Reset. Generated by software directing a command to reset a specific codec back to its default state
An initialization sequence is requested after any of the following three events: 1. 2. 3. Link Reset Codec Reset Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1.
1. 2. 3.
Link Reset
A link reset may be caused by 3 events: The HDA controller asserts RST# for any reason (power up, or PCI reset) Software initiates a link reset via the `CRST' bit in the Global Control Register (GCR) of the HDA controller Software initiates power management sequences. Figure 13, page 19, shows the `Link Reset' timing including the `Enter' sequence ( ~ ) and `Exit' sequence ( ~ )
Enter `Link Reset': Software writes a 0 to the `CRST' bit in the Global Control Register of the HDA controller to initiate a link reset When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low The controller asserts the RST# signal to low, and enters the `Link Reset' state All link signals driven by controller and codecs should be tri-state by internal pull low resistors
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Exit from `Link Reset': If BCLK is re-started for any reason (codec wake-up event, power management, etc.) Software is responsible for de-asserting RST# after a minimum of 100s BCLK running time (the 100sec provides time for the codec PLL to stabilize) Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the last bit of frame SYNC, it means the codec requests an initialization sequence)
Previous Frame 4 BCLK 4 BCLK Link in Reset >=100 usec >= 4 BCLK Initialization Sequence
BCLK SYNC
2 Normal Frame SYNC is absent Driven Low Normal Frame SYNC 8 Driven Low Pulled Low Wake Event 9
Pulled Low
SDOs SDIs RST#
1 3
Driven Low
Pulled Low
Pulled Low 4 5 6 7
Figure 13. Link Reset Timing
7.3.2.
Codec Reset
A `Codec Reset' is initiated via the codec RESET command verb. It results in the target codec being reset to the default state. After the target codec completes its reset operation, an initialization sequence is requested.
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7.3.3.
Codec Initialization Sequence
The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the controller The codec will stop driving the SDI during this turnaround period The controller drives SDI to assign a CAD to the codec The controller releases the SDI after the CAD has been assigned Normal operation state
Exit from Reset Connection Frame Turnaround Frame (Non-48kHz Frame) Address Frame (Non-48kHz Frame) Normal Operation
BCLK SYNC SDIx RST#
1 2 3
Frame SYNC
Frame SYNC
4 5 6 SD14 7 8
Frame SYNC Response
SD0 SD1
Codec Drives SDIx
Codec Turnaround (477 BCLK Max.)
Controller Drives SDIx
Controller Turnaround (477 BCLK Max.)
Codec Drives SDIx
Figure 14. Codec Initialization Sequence
7.4. Verb and Response Format
7.4.1. Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with 12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and controls parameters in the codec.
Bit [39:32] Reserved Table 10. 40-Bit Commands in 4-Bit Verb Format Bit [31:28] Bit [27:20] Bit [19:16] Codec Address Node ID Verb ID Bit [15:0] Payload
Bit [39:32] Reserved
Table 11. 40-Bit Commands in 12-Bit Verb Format Bit [31:28] Bit [27:20] Bit [19:8] Codec Address Node ID Verb ID
Bit [7:0] Payload
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Table 12. Supported Commands Modem Function Group*1 HDMI Function Group*1 Vendor Define Group*1 Audio Function Group Vendor Define Widget Y Y Y Rev. 1.1 Audio Out Converter Audio In Converter
Get parameter Connection Select Get Connection List Entry Processing State Coefficient Index Processing Coefficient Amplifier Gain/Mute Stream Format Digital Converter 1 Digital Converter 2 Power State Channel / Stream ID SDI Select Pin Widget Control Unsolicited Enable Pin Sense EAPD / BTL Enable All GPIO Control
Y 703 5-4-3-Y Y Y 2-Y Y 70D Y Y 70E Y Y 705 Y 706 Y Y 704 707 Y 708 Y 709 Y 70C 71071A Beep Generator Control 70A Volume Knob Control 70F Subsystem ID, Byte 0 720 Y Subsystem ID, Byte 1 721 Y Subsystem ID, Byte 2 722 Y Subsystem ID, Byte 3 723 Y Config Default, Byte 0 71C Y Config Default, Byte 1 71D Y Config Default, Byte 2 71E Y Config Default, Byte 3 71F Y RESET 7FF Y *1: The ALC888S does not support Modem/HDMI/Vendor groups and Power State widgets.
F00 F01 F02 F03 D-C-B-A-F0D F0D F05 F06 F04 F07 F08 F09 F0C F10F1A F0A F0F F20 F20 F20 F20 F1C F1C F1C F1C
Set Verb
Supported Verb
Y 701
Y
Y
Y Y Y
Y Y Y
Y
Y Y Y
Y
Y
Y
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Beep Generator Y Y
Selector Widget
Power Widget*1
Volume Knob
Sum Widget
Pin Widget
Root Node
Get Verb
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ALC888S Datasheet
Table 13. Supported Parameters Modem Function Group*1 HDMI Function Group*1 Vendor Define Group*1 Audio Function Group Vendor Define Widget Y Y Y Rev. 1.1 Audio Out Converter
Audio In Converter
Supported Parameter
Vendor ID 00 Y Revision ID 02 Y Subordinate Node Count 04 Y Y Function Group Type 05 Y 08 Y Audio Function Group Capabilities Audio Widget Capabilities 09 Y Y Y Y Sample Size, Rate 0A Y Y Y Stream Formats 0B Y Y Y Pin Capabilities 0C Y Input Amp Capabilities 0D Y Y Output Amp Capabilities 12 Y Y Connection List Length 0E Y Y Y Supported Power States 0F Y Y Y Y Y Processing Capabilities 10 GPI/O Count 11 Volume Knob Capabilities 13 *1: The ALC888S does not support Modem/HDMI/Vendor groups and Power State widgets.
Y
Y
Y
Y Y Y
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the codec in response to a current command verb. The codec will send Solicited Response data in the next frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by software, opaque to the controller. Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI status information can be actively delivered to the controller and interpreted by software. The `Tag' in Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Bit [35] Valid Table 14. Solicited Response Format Bit [34] Bit [33:32] Unsol=0 Reserved Bit [31:0] Response
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Beep Generator Y
Selector Widget
Power Widget*1
Parameter ID
Volume Knob
Sum Widget
Pin Widget
Root Node
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ALC888S Datasheet
Bit [35] Valid Table 15. Unsolicited Response Format Bit [34] Bit [33:32] Bit [31:28] Unsol=1 Reserved Tag Bit [27:0] Response
Note:
The response stream in the link protocol is 36-bits wide. The response is placed in the lower 32-bit field. Bit-35 is a `Valid' bit to indicate the response is `Ready'. Bit-34 is set to indicate that an unsolicited response was sent.
7.5. Power Management
The ALC888S does not support Wake-Up events when in low-power mode. All power management state changes in widgets are driven by software. Table 16 shows the System Power State Definitions. In the ALC888S, all the widgets, including output/input converters, support power control. Software may have various power states depending on system configuration. Table 17 indicates those nodes that support power management. To simplify power control, software can configure whole codec power states through the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no individual power control to supply fine-grained power control.
Power States D0 D1 D2 D3 (Hot) D3 (Cold) Table 16. System Power State Definitions Definitions All power on. Individual DACs and ADCs can be powered up or down as required All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference stays up All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog reference is off (D1 + analog reference off) Power still supplied. The codec stops the internal clock. State is maintained All power removed. State lost Power Controls in NID 01h D0 D1 D2 Normal Normal Normal Normal PD PD Normal PD PD Normal PD PD Normal PD PD Normal PD PD Normal PD PD Normal PD PD Normal Normal PD Normal Normal PD Normal Normal PD D3 PD PD PD PD PD PD PD PD PD PD PD Link Reset PD PD PD PD PD PD PD PD Normal Normal Normal
Table 17. Description LINK Response Front DAC Surr DAC) Cen/LFE DAC Side DAC Fout DAC LINE ADC MIX ADC All Headphone Drivers All Mixers All Reference Note: PD=Powered Down Item Audio Function (NID=01h)
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Table 18. Powered Down Conditions Description Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with pulled low 47K resistors internally. S/PDIF-IN is also floated. Detection of `Link Reset Entry' and `Link Reset Exit' sequences are supported. All states are maintained if DVDD is supplied Analog block and digital filter are powered down Analog block and digital filter are powered down Analog block and digital filter are powered down Analog block and digital filter are powered down Analog block and digital filter are powered down Analog block and digital filter are powered down. Data on SDATA-IN is quiet Analog block and digital filter are powered down. Data on SDATA-IN is quiet All headphone drivers are powered down All internal mixer widgets are powered down. The DC reference and VREFOUTx at individual pin complexes are still alive All internal references, DC reference, and VREFOUTx at individual pin complexes are off
Condition LINK Response powered down
Front DAC powered down Surr DAC powered down CEN/LFE DAC powered down SIDESURR DAC powered down Fout DAC powered down LINE ADC powered down MIX ADC powered down Headphone Driver powered down Mixers powered down Reference power down
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8.
Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC888S. If a verb is not supported by the addressed widget, it will respond with 32 bits of `0'.
8.1. Verb - Get Parameters (Verb ID=F00h)
The `Get Parameters' verb is used to get system information and the function capabilities of the HDA codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget. Some parameters are supported only in a specific widget.
Table 19. Verb - Get Parameters (Verb ID=F00h) Get Parameter Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=00h Verb ID=F00h Parameter ID[7:0] 32-bit Response Note: If the parameter ID is not supported, the returned response is 32 bits of `0'.
8.1.1.
Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 20. Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h) Codec Response Format Bit Description 31:16 Vendor ID=10ECh (Realtek's PCI vendor ID) 15:0 Device ID=0888h Note: The Root Node (NID=00h) supports this parameter.
8.1.2.
Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 21. Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's 23:20 MajRev. The major version number (in decimal) of the HDA Spec to which the ALC888S is fully compliant 19:16 MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC888S is fully compliant 15:8 Revision ID. The vendor's revision number 00h is for ALC888, 01h is for ALC888S. 7:0 Stepping ID. The vendor's stepping number within the given Revision ID Note: The Root Node (NID=00h in the ALC888S) supports this parameter.
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8.1.3.
Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node.
Table 22. Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's 23:16 Starting Node Number The starting node number in the sequential widgets 15:8 Reserved. Read as 0's 7:0 Total Number of Nodes For a root node, the total number of function groups in the root node For a function group, the total number of widget nodes in the function group
8.1.4.
Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h)
Table 23. Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) Codec Response Format Bit Description 31:9 Reserved. Read as 0's 8 UnSol Capable 0: Unsolicited response is not supported by this function group 1: Unsolicited response is supported by this function group 7:0 Function Group Type 00h: Reserved 01h: Audio Function 02h: Modem Function 03h~7Fh: Reserved 80h~FFh: Vendor Defined Function Note: The Audio Function Group (NID=01h) supports this parameter.
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8.1.5.
Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Table 24. Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) Codec Response Format Bit Description 31:17 Reserved. Read as 0's 16 Beep Generator A `1' indicates the presence of an integrated Beep generator within the Audio Function Group 15:12 Reserved. Read as 0's 11:8 Input Delay 7:4 Reserved. Read as 0's 3:0 Output Delay Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.6.
Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Table 25. Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's 23:20 Widget Type 0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex 5h: Power Widget 6h: Volume Knob Widget 7h~Eh: Reserved Fh: Vendor defined audio widget 19:16 Delay. Samples delayed between the HDA link and widgets 15:11 Reserved. Read as 0's 10 Power Control 0: Power state control is not supported on this widget 1: Power state is supported on this widget 9 Digital 0: An analog input or output converter 1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.) 8 ConnList. Connection List 0: Connected to HDA link. No Connection List Entry should be queried 1: Connection List Entry must be queried 7 UnsolCap. Unsolicited Capable 0: Unsolicited response is not supported 1: Unsolicited response is supported 6 ProcWidget. Processing Widget 0: No processing control 1: Processing control is supported 5 Reserved. Read as 0 4 Format Override 3 AmpParOvr, AMP Param Override 7.1+2 Channel High Definition Audio Codec 27 Track ID: JATR-1076-21 Rev. 1.1
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Codec Response Format Bit Description 2 OutAmpPre. Out AMP Present 1 InAmpPre. In AMP Present 0 Stereo 0: Mono Widget 1: Stereo Widget
8.1.7.
Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Parameters here provide default information about formats. Individual converters have their own parameters to provide supported formats if their `Format Override' bit is set.
Table 26. Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) Codec Response Format Bit Description 31:21 Reserved. Read as 0's 20 B32. 32-bit audio format support 0: Not supported 1: Supported 19 B24. 24-bit audio format support 0: Not supported 1: Supported 18 B20. 20-bit audio format support 0: Not supported 1: Supported 17 B16. 16-bit audio format support 0: Not supported 1: Supported 16 B8. 24-bit audio format support 0: Not supported 1: Supported 15:12 Reserved. Read as 0's 11 R12. 384kHz (=8*48kHz) rate support 0: Not supported 1: Supported 10 R11. 192kHz (=4*48kHz) rate support 0: Not supported 1: Supported 9 R10. 176.4kHz (=4*44.1kHz) rate support 0: Not supported 1: Supported 8 R9. 96kHz (=2*48kHz) rate support 0: Not supported 1: Supported 7.1+2 Channel High Definition Audio Codec 28 Track ID: JATR-1076-21 Rev. 1.1
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Codec Response Format Bit Description 7 R8. 88.2kHz (=2*44.1kHz) rate support 0: Not supported 1: Supported 6 R7. 48kHz rate support 0: Not supported 1: Supported 5 R6. 44.1kHz rate support 0: Not supported 1: Supported 4 R5. 32kHz (=2/3*48kHz) rate support 0: Not supported 1: Supported 3 R4. 22.05kHz (=1/2*44.1kHz) rate support 0: Not supported 1: Supported 2 R3. 16kHz (=1/3*48kHz) rate support 0: Not supported 1: Supported 1 R2. 11.025kHz (=1/4*44.1kHz) rate support 0: Not supported 1: Supported 0 R1. 8kHz (=1/6*48kHz) rate support 0: Not supported 1: Supported
8.1.8.
Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters have their own parameters to provide supported formats if the `Format Override' bit is set.
Table 27. Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Codec Response Format Bit Description 31:3 Reserved. Read as 0's 2 AC3 0: Not supported 1: Supported 1 Float32 0: Not supported 1: Supported 0 PCM 0: Not supported 1: Supported Note: Input converters and output converters support this parameter. 7.1+2 Channel High Definition Audio Codec 29 Track ID: JATR-1076-21 Rev. 1.1
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8.1.9.
Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 28. Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) Codec Response Format Bit Description 31:16 Reserved. Read as 0's 15:8 VREF Control Capability `1' in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of AVDD. 7:6 5 4 3 2 1 0 Reserved 100% 80% Reserved Ground 50% Hi-Z 7 L-R Swap. Indicates the capability of swapping the left and rights 6 Balanced I/O Pin `1' indicates this pin complex has balanced pins 5 Input Capable `1' indicates this pin complex supports input 4 Output Capable `1' indicates this pin complex supports output 3 Headphone Drive Capable `1' indicates this pin complex has an amplifier to drive a headphone 2 Presence Detect Capable `1' indicates this pin complex can detect whether there is anything plugged in 1 Trigger Required `1' indicates whether a software trigger is required for an impedance measurement 0 Impedance Sense Capable `1' indicates this pin complex can perform analog sense on the attached device to determine its type Note: Only Pin Complex widgets support this parameter.
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8.1.10. Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the `AMP Param Override' bit is set.
Table 29. Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) Codec Response Format Bit Description 31 (Input) Mute Capable 30:23 Reserved. Read as 0 22:16 Step Size Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. `0' indicates a step of 0.25dB. `127' indicates a step of 32dB 15 Reserved. Read as 0 14:8 Number of Steps Indicates the number of steps in the gain range. `0' means the gain is fixed 7 Reserved. Read as 0 6:0 Offset Indicates which step is 0dB
8.1.11. Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the `AMP Param Override' bit is set.
Table 30. Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) Codec Response Format Bit Description 31 (Output) Mute Capable 30:23 Reserved. Read as 0 22:16 Step Size Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. `0' indicates a step of 0.25dB. `127' indicates a step of 32dB 15 Reserved. Read as 0 14:8 Number of Steps Indicates the number of steps in the gain range. `0' means the gain is fixed 7 Reserved. Read as 0 6:0 Offset. Indicates which step is 0dB
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8.1.12. Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 31. Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh) Codec Response Format Bit Description 31:8 Reserved. Read as 0 7 Short Form 0: Short Form 1: Long Form 6:0 Connect List Length Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one input, and there is no Connection Select Control (not a MUX widget)
8.1.13. Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Table 32. Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh) Codec Response Format Bit Description 31:4 Reserved. Read as 0's 3 D3Sup 1: Power state D3 is supported 2 D2Sup 1: Power state D2 is supported 1 D1Sup 1: Power state D1 is supported 0 D0Sup 1: Power state D0 is supported
8.1.14. Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Table 33. Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h) Codec Response Format Bit Description 31:16 Reserved. Read as 0's 15:8 NumCoeff. Number of Coefficient 7:1 Reserved. Read as 0's 0 Benign 0: Processing unit is not linear and time invariant 1: Processing unit is linear and time invariant 7.1+2 Channel High Definition Audio Codec 32 Track ID: JATR-1076-21 Rev. 1.1
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8.1.15. Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Table 34. Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Codec Response Format Bit Description 31 GPIWake=0 The ALC888S does not support GPIO wake up function 30 GPIUnsol=1 The ALC888S supports GPIO unsolicited response 29:24 Reserved. Read as 0's 23:16 NumGPIs=00h No GPI pin is supported 15:8 NumGPOs=00h No GPO pin is supported 7:0 NumGPIOs=03h Three GPIO pins are supported
8.1.16. Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Table 35. Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) Codec Response Format for NID=21h (Volume Control Knob) Bit Description 31:0 Reserved. Read as 0's Note: The ALC888S does not support volume knob and will respond with 0's to this parameter.
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8.2. Verb - Get Connection Select Control (Verb ID=F01h)
Table 36. Verb - Get Connection Select Control (Verb ID=F01h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F01h 0's Bit[7:0] are Connection Index
Codec Response for Analog Port-A/B/C/D/E/F/G/H Bit Description 31:8 0's 7:0 Connection Index currently Set (Default value is 00h) 00h: Sum Widget NID=0Ch 01h: Sum Widget NID=0Dh 02h: Sum Widget NID=0Eh 03h: Sum Widget NID=0Fh 04h: Sum Widget NID=26h Other: Reserved
Codec Response for Digital Pin S/PDIF-OUT Bit Description 31:8 0's 7:0 Connection Index currently Set (Default value is 00h) 00h: Digital Converter (S/PDIF-OUT) NID=06h Other: Reserved
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
8.3. Verb - Set Connection Select (Verb ID=701h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 37. Verb - Set Connection Select (Verb ID=701h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=701h Select Index [7:0] 0's for all nodes
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8.4. Verb - Get Connection List Entry (Verb ID=F02h)
Table 38. Verb - Get Connection List Entry (Verb ID=F02h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F02h Offset Index - N[7:0] 32-bit Response Codec Response for NID=08h (LINE ADC) Bit Description 31:8 Connection List Entry (N+3), (N+2) and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 23h (Sum Widget) for N=0~3 Returns 00h for N>3
Codec Response for NID=09h (MIX ADC) Bit Description 15:8 Connection List Entry (N+3), (N+2) and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 22h (Sum Widget) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Ah (S/PDIF-IN Converter) Bit Description 31:8 Connection List Entry (N+3), (N+2) and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3 Returns 00h for N>3
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Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3) Returns 1Bh (Pin Complex - LINE2) for N=0~3 Returns 15h (Pin Complex-SURR) for N=4~7 Returns 00h for N>7 23:16 Connection List Entry (N+2) Returns 1Ah (Pin Complex - LINE1) for N=0~3 Returns 14h (Pin Complex - FRONT) for N=4~7 Returns 00h for N>7 15:8 Connection List Entry (N+1) Returns 19h (Pin Complex - MIC2) for N=0~3. Returns 1Dh (Pin Complex - PCBEEP) for N=4~7 Returns 17h (Pin Complex - SIDESURR) for N=8~11 Returns 00h for N>11 7:0 Connection List Entry (N) Returns 18h (Pin Complex - MIC1) for N=0~3 Returns 1Ch (Pin Complex - CD) for N=4~7 Returns 16h (Pin Complex - CEN/LFE) for N=8~11 Returns 00h for N>11
Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 02h (Front DAC) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7.1+2 Channel High Definition Audio Codec 36 Track ID: JATR-1076-21 Rev. 1.1
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Codec Response for NID=0Dh (Surround Sum) Bit Description 7:0 Connection List Entry (N) Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3.
Codec Response for NID=0Eh (Cen/LFE Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 04h (Cen/LFE DAC) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Fh (Side-Surr Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 05h (Front DAC) for N=0~3 Returns 00h for N>3
Codec Response for NID=26h (Fout Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3
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Codec Response for NID=26h (Fout Sum) Bit Description 7:0 Connection List Entry (N) Returns 25h (Fout1 DAC) for N=0~3 Returns 00h for N>3
Codec Response for NID=14h~1Bh (Port-A to port-H) Bit Description 31:24 Connection List Entry (N+3) Returns 0Fh (Sum Widget NID=0Fh) for N=0~3 Returns 00h for n>3 23:16 Connection List Entry (N+2) Returns 0Eh (Sum Widget NID=0Eh) for N=0~3 Returns 00h for N>3 15:8 Connection List Entry (N+1) Returns 0Dh (Sum Widget NID=0Dh) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 0Ch (Sum Widget NID=0Ch) for N=0~3 Returns 26h (Sum Widget NID=26h) for N=4~7 Returns 00h for N>7
Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT) Bit Description 31:16 Connection List Entry (N+3) and (N+2) Returns 0000h 15:8 Connection List Entry (N+1) Returns 00h 7:0 Connection List Entry (N) Returns 06h (S/PDIF-OUT converter) for N=0~3 Returns 00h for N>3
Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs) Bit Description 31:24 Connection List Entry (N+3) Returns 1Bh (Pin Complex - LINE2) for N=0~3 Returns 15h (Pin Complex-SURR) for N=4~7 Returns 00h for N>7 23:16 Connection List Entry (N+2) Returns 1Ah (Pin Complex - LINE1) for N=0~3 Returns 14h (Pin Complex - FRONT) for N=4~7 Returns 0Bh (Sum Widget) for N=8~11 Returns 00h for N>11 7.1+2 Channel High Definition Audio Codec 38 Track ID: JATR-1076-21 Rev. 1.1
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Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs) Bit Description 15:8 Connection List Entry (N+1) Returns 19h (Pin Complex - MIC2) for N=0~3 Returns 1Dh (Pin Complex - PCBEEP) for N=4~7 Returns 17h (Pin Complex - SIDESURR) for N=8~11 Returns 00h for N>11 7:0 Connection List Entry (N) Returns 18h (Pin Complex - MIC1) for N=0~3 Returns 1Ch (Pin Complex - CD) for N=4~7 Returns 16h (Pin Complex - CEN/LFE) for N=8~11 Returns 00h for N>11
Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h)
8.5. Verb - Get Processing State (Verb ID=F03h)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 39. Verb - Get Processing State (Verb ID=F03h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F03h 0's 32-bit response
Codec Response for All NID Bit Description 31:0 Not supported (returns 00000000h)
8.6. Verb - Set Processing State (Verb ID=703h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 40. Verb - Set Processing State (Verb ID=703h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=703h Processing State [7:0] 0's for all nodes
Codec Response for All NID Bit Description 31:0 0's
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8.7. Verb - Get Coefficient Index (Verb ID=Dh)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 41. Verb - Get Coefficient Index (Verb ID=Dh) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=Dh 0's Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Registers) Bit Description 31:16 Reserved. Read as 0's 15:0 Coefficient Index
Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h)
8.8. Verb - Set Coefficient Index (Verb ID=5h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 42. Verb - Set Coefficient Index (Verb ID=5h) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=5h Coefficient Index [15:0] 0's for all nodes
Codec Response for All NID Bit Description 31:0 0's
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8.9. Verb - Get Processing Coefficient (Verb ID=Ch)
Table 43. Verb - Get Processing Coefficient (Verb ID=Ch) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0] CAd=X Node ID=Xh Verb ID=Ch 0's Processing Coefficient [15:0]
Codec Response for NID=20h (Realtek Defined Registers) Bit Description 31:16 Reserved. Read as 0's 15:0 Processing Coefficient
Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h)
8.10. Verb - Set Processing Coefficient (Verb ID=4h)
Table 44. Verb - Set Processing Coefficient (Verb ID=4h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0] CAd=X Node ID=Xh Verb ID=4h Coefficient [15:0] 0's for all nodes
Codec Response for All NID Bit Description 31:0 0's
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8.11. Verb - Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 45. Verb - Get Amplifier Gain (Verb ID=Bh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:16] Verb ID=Bh Payload Bit [15:0] `Get' payload [15:0] Codec Response Format Response [31:0] Bit[7:0] are responsible for `Get'
`Get' Payload in Command Bit[15:0] Bit Description 15 Get Input/Output 0: Input amplifier gain is requested 1: Output amplifier gain is requested 14 Reserved. Read as 0. 13 Get Left/Right 0: Right amplifier gain is requested 1: Left amplifier gain is requested 12:4 Reserved. Read as 0's 3:0 Index[3:0] for Input Source Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored
Codec Response for 08h (LINE ADC) and 09h (MIX ADC) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in `Get Amplifier Gain': Read as 0. (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from -16.5B~+30dB in 1.5dB steps Bit-15 is 1 in `Get Amplifier Gain': Read as 0's (No Output Amplifier Mute)
Codec Response for NID=0Bh (MIXER Sum Widget) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute. 0: Unmute 1: Mute (Default for all Index) Bit-15 is 1 in `Get Amplifier Gain': Read as 0. (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from -34.5dB~+12dB in 1.5dB steps Bit-15 is 1 in `Get Amplifier Gain': Read as 0's (No Output Amplifier Mute)
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Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/LFE, SIDESURR Sum) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0. (No Input Amplifier Gain) Bit-15 is 1 in `Get Amplifier Gain': Output Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from -46.5dB~0dB in 1.5dB steps
Codec Response for NID=14h~1Bh (Pin Complex: Front/Surr/CenLFE/SIDESURR/MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 Bit-15 is 1 in `Get Amplifier Gain': Output Amplifier Mute, 0:Unmute, 1:Mute (NID=14h~1Bh,Default=1) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0's Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain)
Codec Response to Other NID Bit Description 31:0 Not supported (returns 00000000h)
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ALC888S Datasheet
8.12. Verb - Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 46. Verb - Set Amplifier Gain (Verb ID=3h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=3h Payload Bit [7:0] `Set' payload [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Set' Payload in Command Bit[15:0] Bit Description 15 Set Output Amp 1: Indicates output amplifier gain will be set 14 Set Input Amp 1: Indicates input amplifier gain will be set 13 Set Left Amp 1: Indicates left amplifier gain will be set 12 Set Right Amp 1: Indicates right amplifier gain will be set 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets) 5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector widget. The index is ignored if the node is not a Sum or a Selector widget, or the `Set Input Amp' bit is not set 7 Mute 0: Unmute 1: Mute (- gain) 6:0 Gain[6:0] A 7-bit step value specifying the amplifier gain
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ALC888S Datasheet
8.13. Verb - Get Converter Format (Verb ID=Ah)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 47. Verb - Get Converter Format (Verb ID=Ah) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=Ah 0's Bit[15:0] are converter format
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC, S/PDIF-OUT). Codec Response for NID=08h~0Ah (Input Converters: LINE, MIX DAC, and S/PDIF-IN) Bit Description 31:16 Reserved. Read as 0 15 Stream Type (TYPE) 0: PCM 1: Non-PCM 14 Sample Base Rate (BASE) 0: 48kHz 1: 44.1kHz 13:11 Sample Base Rate Multiple (MULT) 000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved 10:8 Sample Base Rate Divisor (DIV) 000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8 The ALC888S does not support Divisor. Always read as 000b 7 Reserved. Read as 0. 6:4 Bits per Sample (BITS) 000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: reserved 3:0 Number of Channels 0: 1 channel 1: 2 channels 2: 3 channels ..... 15: 16 channels
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.14. Verb - Set Converter Format (Verb ID=2h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 48. Verb - Set Converter Format (Verb ID=2h) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=2h Set format [15:0] 0's for all nodes
`Set' Payload in Command Bit[15:0] Bit Description 31:16 Reserved. Read as 0 15 Stream Type (TYPE) 0: PCM 1: Non-PCM 14 Sample Base Rate (BASE) 0: 48kHz 1: 44.1kHz 13:11 Sample Base Rate Multiple (MULT) 000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved 10:8 Sample Base Rate Divisor (DIV) 000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8 7 Reserved. Read as 0 6:4 Bits per Sample (BITS) 000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved 3:0 Number of Channels 0: 1 channel 1: 2 channels 2: 3 channels ........ 15: 16 channels
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8.15. Verb - Get Power State (Verb ID=F05h)
Table 49. Verb - Get Power State (Verb ID=F05h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Bit [19:8] Verb ID=Ah Payload Bit [7:0] 0's Codec Response Format Response [31:0] Power State [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:6 Reserved. Read as 0's 5:4 PS-Act. Actual Power State [1:0] 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes (NID=01h), PS-Act is always equal to PS-Set 3:2 Reserved. Read as 0's 1:0 PS-Set, Set Power State [1:0] 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Set controls the current power setting of the referenced node
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.16. Verb - Set Power State (Verb ID=705h)
Table 50. Verb - Set Power State (Verb ID=705h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Bit [19:8] Verb ID=705h Payload Bit [7:0] Power State [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Power State' in Command Bit[7:0] Bit Description 7:6 Reserved. Read as 0's 5:4 PS-Act. Actual Power State [1:0] 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node. 3:2 Reserved. Read as 0's 1:0 PS-Set. Set Power State [1:0] 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3
8.17. Verb - Get Converter Stream, Channel (Verb ID=F06h)
Table 49. Verb - Get Converter Stream, Channel (Verb ID=F06h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F06h 0's Stream & Channel [7:0]
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC, S/PDIF-OUT) Codec Response for NID=08h~0Ah (Input Converters: LINE ADC, MIX DAC, and S/PDIF-IN) Bit Description 31:8 Reserved. Read as 0's 7:4 Stream[3:0] The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 3:0 Channel[3:0] The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h) 7.1+2 Channel High Definition Audio Codec 48 Track ID: JATR-1076-21 Rev. 1.1
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ALC888S Datasheet
8.18. Verb - Set Converter Stream, Channel (Verb ID=706h)
Table 51. Verb - Set Converter Stream, Channel (Verb ID=706h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=706h Stream & Channel [7:0] 0's for all nodes
`Stream and Channel' in Command Bit[7:0] Bit Description 31:8 Reserved. Read as 0's 7:4 Set Stream[3:0] The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 1:0 Set Channel[3:0] The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel Note: This verb assigns stream and channel for output converters (NID=02h~06h, 25h) and input converters (NID=08h~0Ah). Other widgets will ignore this verb.
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8.19. Verb - Get Pin Widget Control (Verb ID=F07h)
Table 52. Verb - Get Pin Widget Control (Verb ID=F07h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F07h 0's Pin Control [7:0]
Codec Response for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 1Fh (Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT and S/PDIF-IN) Bit Description 31:1 Reserved. Read as 0's 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit) 0: Disabled 1: Enabled 6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit) 0: Disabled 1: Enabled 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit) 0: Disabled 1: Enabled 4: Reserved 2:0 VrefEn (Vrefout Enable Control) 000b: Hi-Z (Disabled) 001b: 50% of AVDD 010b: Ground 0V 011b: Reserved 100b: 80% of AVDD 101b: 100% of AVDD 110b~111b: Reserved Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.20. Verb - Set Pin Widget Control (Verb ID=707h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 53. Verb - Set Pin Widget Control (Verb ID=707h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=707h Pin Control [7:0] 0's for all nodes
`Pin Control' in command [7:0] for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 1Fh: (Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT and S/PDIF-IN) Bit Description 31:1 Reserved. Read as 0's 7 H-Phn Enable 0: Disabled 1: Enabled 6 Out Enable 0: Disabled 1: Enabled 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit) 0: Disabled 1: Enabled 4: Reserved 2:0 VrefEn (Vrefout Enable Control) 000b: Hi-Z (Disabled) 001b: 50% of AVDD 010b: Ground 0V 011b: Reserved 100b: 80% of AVDD) 101b: 100% of AVDD 110b~111b: Reserved
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8.21. Verb - Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an unsolicited response to inform software of a real-time event.
Table 54. Verb - Get Unsolicited Response Control (Verb ID=F08h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID= F08h 0's 32-bit Response
Codec Response for NID=01h (GPIO), 14h~1Bh (Port A to H) Bit Description 31:8 Reserved. Read as 0's 7 Unsolicited Response is Enabled 0: Disabled 1: Enabled 6:4 Reserved. Read as 0's 3:0 Assigned Tag for Unsolicited Response The tag[3:0] is assigned by software to determine which widget generates unsolicited responses Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
8.22. Verb - Set Unsolicited Response Control (Verb ID=708h)
Enables a widget to generate an unsolicited response.
Table 55. Verb - Set Unsolicited Response Control (Verb ID=708h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=708h EnableUnsol [7:0] 0's for all nodes
`EnableUnsol' in Command Bit[7:0] for NID=01h (GPIO), 14h~1Bh (Port A to H) Bit Description 31:8 Reserved. Read as 0's 7 Enable Unsolicited Response 0: Disable 1: Enable 6:4 Reserved. Read as 0's 3:0 Tag for Unsolicited Response Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited responses 7.1+2 Channel High Definition Audio Codec 52 Track ID: JATR-1076-21 Rev. 1.1
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ALC888S Datasheet
8.23. Verb - Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 56. Verb - Get Pin Sense (Verb ID=F09h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID= F09h Payload Bit [7:0] 0's Codec Response Format Response [31:0] 32-bit Response
Codec Response for NID = 14h~1Bh, 1Eh, 1Fh Bit Description 31 Presence Detect Status 0: No device is attached to the pin 1: Device is attached to the pin 30:0 Measured Impedance The ALC888S does not support hardware impedance detection. This field is read as 0's.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
8.24. Verb - Execute Pin Sense (Verb ID=709h)
Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 57. Verb - Execute Pin Sense (Verb ID=709h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID= 709h Right Channel[0] 0's for all nodes
`Payload' in Command Bit[7:0] Bit Description 7:1 Reserved. Read as 0's 0 Right (Ring) Channel Select 0: Sense Left channel (Tip) 1: Sense Right channel (Ring) The ALC888S does not support hardware impedance sensing and will ignore this control.
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8.25. Verb - Get Configuration Default (Verb ID=F1Ch)
Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 58. Verb - Get Configuration Default (Verb ID=F1Ch) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID= F1Ch 0's 32-bit Response
Codec Response for NID=14h, 15h, 16h, 17h, 18h, 19h, 1Ah, 1Bh, 1Eh, and 1Fh Bit Description 31:0 32-bit configuration information for each pin widget Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function Reset Verb).
8.26. Verb - Set Configuration Default Bytes 0, 1, 2, 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and 1Eh~1Fh such as placement and expected default device.
Table 59. Verb - Set Configuration Default Bytes 0, 1, 2, 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Label [7:0] 0's for all nodes Verb ID=71Ch, 71Dh, 71Eh, 71Fh Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb.
Codec Response for All NID Bit Description 31:0 0's
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ALC888S Datasheet
8.27. Verb - Get BEEP Generator (Verb ID=F0Ah)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 60. Verb - Get BEEP Generator (Verb ID= F0Ah) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID= F1Bh 0's Divider [7:0]
`Response' for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:0 Frequency Divider, F[7:0] The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0] The lowest tone is 48kHz/(255*4)=47Hz The highest tone is 48kHz/(1*4)=12kHz A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input
Codec Response for Other NID Bit Description 31:0 0's
8.28. Verb - Set BEEP Generator (Verb ID=70Ah)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 61. Verb - Set BEEP Generator (Verb ID= 70Ah) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=71Bh Divider [7:0] 0's for all nodes
`Divider' in Set Command Bit Description 31:8 Reserved 7:0 Frequency Divider, F[7:0] The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0] The lowest tone is 48kHz/(255*4)=47Hz The highest tone is 48kHz/(1*4)=12kHz A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Codec Response for All NID Bit Description 31:0 0's 7.1+2 Channel High Definition Audio Codec 55 Track ID: JATR-1076-21 Rev. 1.1
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ALC888S Datasheet
8.29. Verb - Get GPIO Data (Verb ID=F15h)
Table 62. Verb - Get GPIO Data (Verb ID= F15h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=F15h Payload Bit [7:0] 0's Codec Response Format Response [31:0] 32-bit Response
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 GPIO[7:3] Data. Not supported in the ALC888S 2:0 GPIO[2:0] Data The value written (output) or sensed (input) on the corresponding pin if it is enabled
Codec Response for Other NID Bit Description 31:0 0's
8.30. Verb - Set GPIO Data (Verb ID=715h)
Table 63. Verb - Set GPIO Data (Verb ID= 715h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=715h Payload Bit [7:0] Data [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Data' in Set command for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 GPIO[7:3] output Data. Not supported in the ALC888S 2:0 GPIO[2:0] Output Data The value written determines the value driven on a pin that is configured as an output pin
Codec Response for All NID Bit Description 31:0 0's
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8.31. Verb - Get GPIO Enable Mask (Verb ID=F16h)
Table 64. Verb - Get GPIO Enable Mask (Verb ID= F16h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F16h 0's EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 Reserved 2:0 GPIO[2:0] Enable mask 0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID Bit Description 31:0 0's
8.32. Verb - Set GPIO Enable Mask (Verb ID=716h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 65. Verb - Set GPIO Enable Mask (Verb ID=716h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=716h Enable Mask [7:0] 0's for all nodes
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 GPIO[7:3] Enable Mask. Not supported in the ALC888S 2:0 GPIO[2:0] Enable Mask 0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID Bit Description 31:0 0's
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8.33. Verb - Get GPIO Direction (Verb ID=F17h)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 66. Verb - Get GPIO Direction (Verb ID=F17h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F17h 0's Direction [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 GPIO[7:3] Direction Control. Not supported in the ALC888S 2:0 GPIO[2:0] Direction Control 0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID Bit Description 31:0 0's
8.34. Verb - Set GPIO Direction (Verb ID=717h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 67. Verb - Set GPIO Direction (Verb ID=717h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=717h Direction [7:0] 0's for all nodes
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 GPIO[7:3] Direction Control. Not supported in the ALC888S 2:0 GPIO[2:0] Direction Control 0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID Bit Description 31:0 0's
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8.35. Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Table 68. Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F19h 0's UnsolEnable [7:0] Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 GPIO[7:3] Unsolicited Enable Mask. Not supported in the ALC888S 2:0 GPIO[2:0] Unsolicited Enable mask 0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Codec Response for Other NID Bit Description 31:0 0's
8.36. Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Table 69. Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=719h UnsolEnable [7:0] 0's for all nodes Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:3 GPIO[7:3] Unsolicited Enable Mask. Not supported in the ALC888S 2:0 GPIO[2:0] Unsolicited Enable Mask 0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Note 2: The unsolicited response of corresponding GPIO is enabled when it's `Enable Mask' and Verb-`Unsolicited Response' for NID=01h are enabled. Codec Response for Other NID Bit Description 31:0 0's 7.1+2 Channel High Definition Audio Codec 59 Track ID: JATR-1076-21 Rev. 1.1
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ALC888S Datasheet
8.37. Verb - Function Reset (Verb ID=7FFh)
Table 70. Verb - Function Reset (Verb ID=7FFh) Command Format (NID=01H) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=7FFh 0's 0's
Codec Response Bit Description 31:0 Reserved. Read as 0's Note: The Function Reset command causes all widgets in the ALC888S to return to their power on default state.
8.38. Verb - Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Table 71. Verb - Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F0Dh/ 0's Bit[31:16]=0's, Bit[15:0] are SIC bit F0Eh
NID=06h (S/PDIF-OUT) Response to `Get verb' - F0Dh (Control 1 for SIC bit[15:0]) NID=06h (S/PDIF-OUT) Response to `Get verb' - F0Eh (Control 2 for SIC bit[15:0]) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 31:16 Read as 0's 15 Reserved. Read as 0's 14:8 CC[6:0] (Category Code) 7 LEVEL (Generation Level) 6 PRO (Professional or Consumer format) 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright) 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis) 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame) 1 V for Validity Control (control V bit and data in Sub-Frame) 7.1+2 Channel High Definition Audio Codec 60 Track ID: JATR-1076-21 Rev. 1.1
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NID=06h (S/PDIF-OUT) Response to `Get verb' - F0Dh (Control 1 for SIC bit[15:0]) NID=06h (S/PDIF-OUT) Response to `Get verb' - F0Eh (Control 2 for SIC bit[15:0]) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 0 Digital Enable. DigEn 0: OFF 1: ON
NID=0Ah (S/PDIF-IN) Response to `Get verb (F0Dh) NID=0Ah (S/PDIF-IN) Response to `Get verb (F0Eh) Bit Description (part of S/PDIF-IN Channel Status) 31:16 Reserved. Read as 0's 15 Reserved. Read as 0's 14:8 CC[6:0] (Category Code) 7 LEVEL (Generation Level) 6 PRO (Professional or Consumer format) 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright) 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis) 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 Reserved 1 In`V'alid. V bit in sub-frame of S/PDIF-IN 0: Data X and Y are valid, or S/PDIF-IN is not locked 1: At least one of data X and Y is invalid 0 Digital Enable. DigEn 0: OFF 1: ON
Codec Response for Other NID Bit Description 31:0 0's
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8.39. Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Table 72. Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) Set Command Format (Verb ID=70Xh, Set Control 1) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=70Dh SIC [7:0] 0's
Set Command Format (Verb ID=70Yh, Set Control 2) Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] CAd=X Node ID=Xh Verb ID=70Eh SIC [15:8]
Codec Response Format Response [31:0] 0's
`Payload' in Set Control 1 for NID=06h (S/PDIF-OUT) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7 LEVEL (Generation Level) 6 PRO (Professional or Consumer format) 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright) 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis) 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame) 1 V for Validity Control (control V bit and data in Sub-Frame) 0 Digital Enable. DigEn 0: OFF 1: ON
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`Payload' in Set Control 2 for NID=06h (S/PDIF-OUT) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7 Reserved. Read as 0's 6:0 CC[6:0] (Category Code)
`Payload' in Set Control 1 for NID=0Ah (S/PDIF-IN) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7:1 Reserved 0 Digital Enable. DigEn 0: OFF 1: ON
`Payload' in Set Control 2 for NID=0Ah (S/PDIF-IN) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7:0 Reserved. Read as 0's Note: Other widgets will ignore this verb.
8.40. Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/D22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 73. Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd = X Node ID=01h Verb ID=F20h 0's 32-bit Response
Codec Response for NID=01h Bit Description 31:16 Subsystem ID[23:8]. (Default=10ECh) 15:8 Subsystem ID[7:0]. (Default=08h). 7:0 Assembly ID[7:0]. (Default=88h).
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8.41. Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Table 74. Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0]) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd = X Node ID=01h Verb ID=723h, Label [7:0] 0's for all nodes 722h, 721h, 720h
Codec Response for all NID Bit Description 0's 31:0
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9.
9.1.1.
Electrical Characteristics
Absolute Maximum Ratings
Table 75. Absolute Maximum Ratings Symbol Minimum Typical DVDD DVDD-IO* AVDD** Ta Ts 3.0 1.5 3.3 0 3.3 3.3 5.0 Maximum 3.6 3.6 5.5 +70 Units V V V o C
9.1. DC Characteristics
o +125 C ESD (Electrostatic Discharge) Susceptibility Voltage All Pins 4500V (Human Body Mode) Note*: The digital link power DVDD-IO must be lower than the digital core power DVDD. Note** : The standard testing condition before shipping is AVDD = 5.0V unless specified. Customer designing with a different AVDD should contact Realtek technical support representatives for special testing support.
Parameter Power Supply: Digital power for core Digital power for HDA link Analog Ambient Operating Temperature Storage Temperature
9.1.2.
Threshold Voltage
Table 76. Threshold Voltage Symbol Minimum Typical Vin -0.30 VIL VIH VIL VIH VOH VOL 0.65* DVDDIO 0.56* DVDD (1.85) 0.9*DVDD -10 -10 5 50k
DVDD= 3.3V5%, Tambient=25C, with 50pF external load.
Parameter Input Voltage Range Low Level Input Voltage (HDA link) High Level Input Voltage (HDA link) Low Level Input Voltage (S/PDIF-IN/OUT, GPIOs) High Level Input Voltage (S/PDIF-IN/OUT, GPIOs) High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current (Hi-Z) Output Buffer Drive Current Internal Pull Up Resistance Maximum DVDD +0.30 0.30* DVDDIO 0.44*DVDD (1.45) 0.1*DVDD 10 10 Units V V V V V V V A A mA
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9.1.3.
Digital Filter Characteristics
Maximum 0.45*Fs 0.45*Fs Units kHz kHz dB dB kHz kHz dB dB
Table 77. Digital Filter Characteristics Filter Description Minimum Typical ADC Lowpass Filter Passband 0 Stopband 0.60*Fs Stopband Rejection -76.0 Passband 0.02 Frequency Response DAC Lowpass Filter Passband 0 Stopband 0.60*Fs Stopband Rejection -78.5 Passband 0.020 Frequency Response Note: Fs=Sample rate
9.1.4.
S/PDIF Input/Output Characteristics
DVDD= 3.3V, Tambient=25C, with 75 external load.
Table 78. S/PDIF Input/Output Characteristics Parameter Symbol Minimum Typical Maximum S/PDIF-OUT High Level Output VOH 3.0 3.3 S/PDIF-OUT Low Level Output VOL 0 0.3 S/PDIF-IN High Level Input VIH 1.85 S/PDIF-IN Low Level Input VIL 1.45 S/PDIF-IN Bias Level Vt 1.65 Units V V V V V
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9.2. AC Characteristic
9.2.1. Link Reset and Initialization Timing
Maximum 1 Units s s Frame Time Table 79. Link Reset and Initialization Timing Parameter Symbol Minimum Typical RESET# Active Low Pulse Width TRST 1.0 RESET# Inactive to BCLK TPLL 20 Startup delay for PLL ready time SDI Initialization Request TFRAME -
4 BCLK
4 BCLK
>= 4 BCLK
Initialization Sequence
BCLK SYNC SDO SDI
Initialization Request Normal Frame SYNC
RESET#
TRST TPLL T FRAME
Figure 15. Link Reset and Initialization Timing
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9.2.2.
Link Timing Parameters at the Codec
Units MHz ns ns ns (%) ns (%) ns ns ns ns
Table 80. Link Timing Parameters at the Codec Symbol Minimum Typical Maximum 24.0 Tcycle 41.67 Tjitter 2.0 Thigh 18.75 22.91 (45%) (55%) BCLK Low Pulse Width Tlow 18.75 22.91 (45%) (55%) Tsetup 2.1 SDO Setup Time at Both Rising and Falling Edge of BCLK Thold 2.1 SDO Hold Time at Both Rising and Falling Edge of BCLK Ttco 7.5 8.0 SDI Valid Time After Rising Edge of BCLK (1: 50pF external load) SDI Flight Time Tflight 2.0 Parameter BCLK Frequency BCLK Period BCLK Jitter BCLK High Pulse Width
T_cycle T_high
BCLK
V IH VT V IL T_setup T_hold T_low
SDO
T_tco VOH
SDI
VOL T_flight
Figure 16. Link Signals Timing
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9.2.3.
S/PDIF Output and Input Timing
Maximum 4 169.2 (52%) 169.2 (52%) 10 179 (55%) 179 (55%) Units MHz ns ns ns (%) ns (%) ns ns ns ns ns (%) ns (%)
Table 81. S/PDIF Output and Input Timing Parameter Symbol Minimum Typical S/PDIF-OUT Frequency 3.072 *1 S/PDIF-OUT Period Tcycle 325.6 S/PDIF-OUT Jitter Tjitter S/PDIF-OUT High Level Width THigh 156.2 (48%) 162.8 (50%) S/PDIF-OUT Low Level Width TLow 156.2 (48%) 162.8 (50%) S/PDIF-OUT Rising Time Trise 2.0 S/PDIF-OUT Falling Time Tfall 2.0 S/PDIF-IN Period *2 Tcycle 325.6 S/PDIF-IN Jitter Tjitter S/PDIF-IN High Level Width THigh 146.4 (45%) 162.8 (50%) S/PDIF-IN Low Level Width TLow 146.4 (45%) 162.8 (50%) *1: Bit parameters for 48kHz sample rate of S/PDIF-OUT *2: Bit parameters for 48kHz sample rate of S/PDIF-IN
Tcycle Thigh VIH VIL Trise T fall V OL Tlow VOH Vt
Figure 17. Output and Input Timing
9.2.4.
Test Mode
The ALC888S does not support codec test mode or Automatic Test Equipment (ATE) mode.
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9.3. Analog Performance
Standard Test Conditions * * * Tambient=25 oC, DVDD=3.3V 5%, AVDD=5.0V5% 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms 10K/50pF load; Test bench Characterization BW:10Hz~22kHz
Max Units Vrms Vrms Vrms Vrms dB FSA dB FSA dB FSA dB FS dB FS dB FS Hz Hz dB dB dB dB K mA mA mA mA V mA
Table 82. Analog Performance Parameter Min Typical Full Scale Input Voltage All Inputs (gain=0dB) 1.6 ADC 1.1 Full Scale Output Voltage DAC 1.4 1.0 Headphone Amplifier Output@32 Load S/N (A Weighted) ADC 90 DAC 97 97 Headphone Amplifier Output@32 Load THD+N ADC -86 DAC -92 -78 Headphone Amplifier Output@32 Load Frequency Response ADC 10 DAC 0 Power Supply Rejection -40 Total Out-of-Band Noise (28.8kHz~100kHz) -60 Amplifier Gain Step 1.5 Crosstalk Between Input Channels -80 Input Impedance (gain=0dB) 47 Output Impedance Amplified Output 1 Non-amplified Output 100 Digital Power Supply Current (normal operation) DVDD=3.3V Digital Power Supply Current (power down mode) DVDD=3.3V Analog Power Supply Current (normal operation) AVDD=5.0V Analog Power Supply Current (power down mode) AVDD=5.0V VREFOUTx Output Voltage VREFOUTx Output Current Note: Fs=Sample Rate 7.1+2 Channel High Definition Audio Codec 2.25 40 1.6 51 1.4 2.50 5
0.45*Fs 0.45*Fs 3.75 -
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10. Application Circuits
The ALC888S is pin-to-pin compatible with the ALC8xx series of products. A board designed for the ALC8xx can utilize the ALC888S directly. To get the best compatibility in hardware design and software driver, any modification should be confirmed by Realtek. Realtek may update the latest application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.
10.1. Filter Connection
Figure 18. Filter Connection
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10.2. Onboard Front Panel Header Connection
Option 1 in Figure 19 comes from by Intel's front panel IO connectivity design guide. A drawback of this option is that the ports connected to the front panel must use the same jack detection pin. According to the HD Audio standard specification, ports A/B/C/D use `Sense A' as the jack detect pin; ports E/F/G/H use `Sense B' as the jack detect pin. This is not a good option when the system integrators want to use port-A (pin 39/41) and port-F (pin 16/17) to be the front panel ports, as `Sense A' and `Sense B' cannot be tied together. Option 2 in Figure 19 shows an alternative front panel header design that is also compatible with standard front panel I/O cable. The option 2 header design lets the two ports use an individual sense pin, and is compatible with current HD Audio front panel cable.
Option 1: Follow Intel's HD Audio front panle header design (Two ports must be in the same jack detect group)
MIC2-VREFO D3 1N4148 R11 4.7K MIC2-L MIC2-R LINE2-R LINE2-L C35 C37 C38 C39 1u 1u 100u 100u J3 1 3 5 7 9 CON10A 2 4 6 8 10 MIC2-JD Key PRESENCE# System GPI FIO-SENSE R18 JACK 7 FIO-PORT2-R FIO-PORT2-L L14 L15 FERB FERB C41 C42 100P PORT2-SENSE-RETURN 4 3 5 2 1 FIO-PORT2 (Jack-E) D4 1N4148 R12 4.7K R14 10K +3.3VD FIO-PORT1-L FIO-PORT1-R FIO-PORT2-R FIO-SENSE FIO-PORT2-L
HD Audio Front Panel I/O Cable
J2 1 3 5 7 9 CON10A 2 4 6 8 10 FIO-PRESENCE# PORT1-SENSE -RETURN PORT2-SENSE -RETURN
KEY
+
FRONT-IO-JD
LINE2-JD R19
+
Onboard front panel header
39.2K,1%
20K,1%
Option 2: A more flexible front panel header (Each port can be in different jack detect group)
MIC2-VREFO D5 1N4148 R20 4.7K MIC2-L MIC2-R LINE2-R LINE2-L C44 C46 C48 C51 1u 1u 100u 100u J5 1 3 5 7 9 CON10A 2 4 6 8 10 R25 Key R26 D6 1N4148 R21 4.7K R23 10K PRESENCE# System GPI FIO-PORT1-R FIO-PORT1-L L16 L17 +3.3VD
100P
FIO-SENSE JACK 8 FERB FERB C49 Sense B Sense B 100P C50 100P PORT1-SENSE -RETURN 4 3 5 2 1 FIO-PORT1 (Jack-F)
20K,1%
MIC2-JD LINE2-JD
+
+
Onboard front panel header
39.2K,1%
Figure 19. Front Panel Header Connection
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10.3. Jack Connection on Rear Panel
MIC1-VREFO-L MIC1-VREFO-R R234 4.7K MIC1-R MIC1-L C219 1u C221 1u R235 4.7K L70 L73 FERB FERB C224 100P C225 100P MIC1-JD JACK 30 JACK 31 4 3 5 2 1 MIC-IN (Port-B) SURR-R SURR-L C218 1u C220 1u L69 L72 SURR-JD FERB FERB C222 100P C223 100P 4 3 5 2 1 SURROUND (Port-A)
2.2~4.7uF for DA (LF) frequence response
FRONT-JD FRONT-R FRONT-L C231 C233 100u 100u L75 L77 FERB FERB C236 100P C237 100P +
JACK 33 4 3 5 2 1 FRONT-OUT (Port-D) LFE CEN C228 1u C232 1u L74 L76
CEN-JD FERB FERB C234 C235 100P
JACK 32 4 3 5 2 1 CENTER/LFE (Port-G)
+
2.2~4.7uF for DA (LF) frequence response
100P
LINE1-JD LINE1-R LINE1-L C239 1u C241 1u L78 L80 FERB FERB C245 100P C246 100P
JACK 34 4 3 5 2 1 LINE-IN (Port-C) SIDE-R SIDE-L C240 1u C242 1u L79 L81
JACK 35 SIDESURR-JD FERB FERB C247 C248 100P 4 3 5 2 1 SIDESURR (Port-H)
2.2~4.7uF for DA (LF) frequence response
100P
Figure 20. Jack Connection on Rear Panel
10.4. S/PDIF Input/Output Connection
S/PDIF module option 1: Optical S/PDIF option 2: RCA only
U23 TOTX178
S/PDIF option 3: Optical & RCA
U24 TOTX178 U25 TORX178S
Transmitter
5 GND
S/PDIF-OUT
1 J26 C262 100P 2 R258 100 R259 220
C261 S/PDIF-OUT 0.01u 4 3 2 VCC 5 1 GND
Transmitter
4 3 2 GND VCC 5 OUT 1
Receiver
4 3 2 VCC
1
RCA
IN
IN
R260 10 C264 0.1u L86 47uH C265 0.1u
S/PDIF-OUT
+5VD
C263 0.1u +3.3VD
+5VD
+5VD
U26
TORX178S
+3.3VD R261
Receiver
S/PDIF-IN
5 1 C267 0.01u J28 C269 100P R271 75
12K@ALC882;NC@ALC888/883 R264 10 R266 S/PDIF-IN
S/PDIF-OUT
1 C270 100P R263 100 R267 220
C266 0.01u
4 3 2 GND VCC
S/PDIF-OUT
S/PDIF-IN
R262 R S 12K@ALC882;NC@ALC888/883 C268 0.01u R270 75 R265 10 R268 S/PDIF-IN
1
R269 10 S/PDIF-IN L87 47uH C272 0.1u
RCA
2
J27
10K@ALC882,NC@ALC883
RCA
2
J5A3 RCA G
OUT
C271 100P
10K@ALC882,NC@ALC888/8833
+5VD
J5A is RCA jack with switch
Figure 21. S/PDIF Input/Output Connection
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10.5. Secondary S/PDIF-OUT Connected to HDMI Tx Connector
U3 RCA to HDMI Tx 1 C31 100p 2 R70 200 R69 100 C13 S/PDIF-OUT2 0.01u
Figure 22. Secondary S/PDIF-OUT Connected to HDMI Tx Connector
10.6. Differential Analog CD Used as Line Level Input
CD-JD-Jack CD-R-Jack CD-L-Jack L98 L99 FERB FERB C294 100P C293 100P JACK 41 4 3 5 2 1 CD-IN (9th Port)
Figure 23. Differential Analog CD Used as Line Level Input
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11. Mechanical Dimensions
L L1
SYMBOL
A A1 A2 c D D1 D2 E E1 E2 b e TH L L1
MILLIMETER MIN. TYP MAX. 1.60 0.05 0.15 1.35 1.40 1.45 0.09 0.20 9.00 BSC 7.00 BSC 5.50 9.00 BSC 7.00BSC 5.50 0.17 0.20 0.27 0.50 BSC o 0 3.5o 7o 0.45 0.60 0.75 1.00
INCH MIN. TYP MAX 0.063 0.002 0.006 0.053 0.055 0.057 0.004 0.008 0.354 BSC 0.276 BSC 0.217 0.354 BSC 0.276 BSC 0.217 0.007 0.008 0.011 0.0196 BSC o 0 3.5o 7o 0.018 0.0236 0.030 0.0393
TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm LEADFRAME MATERIAL APPROVE DOC. NO. VERSION 02 CHECK DWG NO. PKGC-065 DATE REALTEK SEMICONDUCTOR CORP.
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12. Ordering Information
Table 83. Ordering Information Part Number Description Status ALC888S-GR LQFP-48 with `Green' package Production Note 1: See page 6 for `Green' package and version identification. Note 2: Above parts are tested under AVDD=5.0V. Customers requesting lower AVDD support should contact Realtek sales representatives or agents.
Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-557-6047 www.realtek.com.tw
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